Multiprocessor interrupt control

Details Multiprocessor interrupt control Multiprocessor interrupt control

G - Physics

06

F

354/230.82

G06F 9/46 (2006.01) G06F 13/26 (2006.01)

Patent

CA 2026770

ABSTRACT Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

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