Multiprocessor interrupt rerouting mechanism

Details Multiprocessor interrupt rerouting mechanism Multiprocessor interrupt rerouting mechanism

G - Physics

06

F

354/230.82

G06F 15/16 (2006.01) G06F 9/50 (2006.01) H04L 29/00 (2006.01) G06F 11/00 (2006.01) G06F 11/20 (2006.01)

Patent

CA 1288524

ABSTRACT A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed, information regarding the status of the communication task. If for any reason the requesting processor being interrupted is inoperative or too busy to handle the interrupt request, the application process is then notified as to the status of the communication task by rerouting the interrupt request from the controller so that another processor can handle it.

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