G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.85
G06F 9/46 (2006.01) G06F 13/26 (2006.01)
Patent
CA 1143852
MULTIPROCESSOR MECHANISM FOR HANDLING CHANNEL INTERRUPTS Abstract The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt con- troller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a correspond- ing queue bit position in the pending register and con- trols the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty. A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs. In each CP, acceptance determining circuits connect to the broad- cast bus and accept the highest-priority-unmask non- empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state. Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queu at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP. An inhibit register in the interrupt controller in the SC inhibits selected bits on the broad- cast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends it acceptance of the P09-79-011 corresponding queue, so that any CP can select the next entry on the corresponding queue. When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state. PO9-79-011
360340
Christensen Neal T.
Van Loo William C.
Werner Robert H.
Wetzel Joseph A.
Zeitler Carl
International Business Machines Corporation
Saunders Raymond H.
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