Multiprocessor system

G - Physics – 06 – F

Patent

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354/231

G06F 1/12 (2006.01) G06F 9/45 (2006.01) G06F 15/167 (2006.01)

Patent

CA 2011503

ABSTRACT A number of synchronization controllers are provided for a multiprocessor system, one controller being provided for each processor and all being commonly connected to a synchronization signal bus. Each of these synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor and transmitting a synchronization wait signal to the synchronization signal bus. Each controller also includes: (a) a synchronization register for specifying the other processors to be synchronized with the corresponding processor; (b) a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization register; and (c) a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of the comparison by the comparator means.

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