Multiprocessor system and interrupt arbiter thereof

Details Multiprocessor system and interrupt arbiter thereof Multiprocessor system and interrupt arbiter thereof

G - Physics

06

F

G06F 9/46 (2006.01) G06F 9/50 (2006.01) G06F 13/26 (2006.01) G06F 15/16 (2006.01)

Patent

CA 2061127

In a tightly coupled multiprocessor system, I/O interrupts are distributed to respective processors in accordance with load conditions of the processors. Interrupt arbitration circuits provided in respective processors receive an interrupt request from an I/O device, effect interrupt arbitration using a parameter indicating the load condition of each processor as a first interrupt priority PPR. If the arbitration fails to determine a sole processor, additional arbitration finally selects a sole processor on the basis of the second interrupt priority RRPR which is variable circularly.

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