Multiprocessor system and message passing controller thereof

Details Multiprocessor system and message passing controller thereof Multiprocessor system and message passing controller thereof

G - Physics

06

F

G06F 13/00 (2006.01) G06F 13/36 (2006.01) G06F 15/16 (2006.01) G06F 15/80 (2006.01)

Patent

CA 2059920

JA9-90-525 MULTIPROCESSOR SYSTEM AND MESSAGE PASSING CONTROLLER THEREOF ABSTRACT Upon requesting message passing, a processor notifies the request to another processor by designating identifiers of candidate destination processors and the upper limit UNR and the lower limit LNR of the number of destination processors. A counter counts acknowledge signals from the candidate destination processors. A comparator compares the count value with the lower and higher limit values. If the count value is not less than the lower limit value, the sending processor determines that it can perform message passing and selects processors, as many as the upper limit number, from the candidate destination processors according to a rule; then initiates the message passing to the processor thus selected.

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