N-channel clamp for esd protection in self-aligned silicided...

Details N-channel clamp for esd protection in self-aligned silicided... N-channel clamp for esd protection in self-aligned silicided...

H - Electricity

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H01L 29/76 (2006.01) H01L 23/60 (2006.01) H01L 27/00 (2006.01) H01L 27/02 (2006.01) H01L 29/45 (2006.01)

Patent

CA 2039777

N-CHANNEL CLAMP FOR ESD PROTECTION IN SELF-ALIGNED SILICIDED CMOS PROCESS ABSTRACT OF THE DISCLOSURE An electrostatic discharge (ESD) protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. FIGURE 2

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