Napnop circuit for conserving power in computer systems

Details Napnop circuit for conserving power in computer systems Napnop circuit for conserving power in computer systems

G - Physics

06

F

G06F 1/32 (2006.01) G06F 9/30 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2110068

ABSTRACT OF THE DISCLOSURE A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.

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