Network and protocol for real-time control of machine...

G - Physics – 06 – F

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354/222

G06F 11/10 (2006.01) H04L 12/00 (2006.01) H04L 12/40 (2006.01)

Patent

CA 2004323

A communication network is comprised of a first, second, third and fourth controller node in line communication. Each controller node includes a microprocessor. Each microprocessor is programmable to respond to and generate data message bytes, each data byte having one start bit, eight data bits, one programmably settable bit and one stop bit. Each microprocessor is further programmable to respond only to a unique address-command data message byte from a message source node. The address-command byte is recognised because the settable bit is set. Each microprocessor is programmed to generate a reply message byte with the ninth bit not set and to then receive from the source node a message count byte followed uninterrupted by the data message bytes. Upon receiving a complete data message conforming to the received count of the count byte, the microprocessor then generates an acknowledgement byte.

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