Next address generation logic in a data processing system

Details Next address generation logic in a data processing system Next address generation logic in a data processing system

G - Physics

06

F

354/230.81

G06F 9/06 (2006.01) G06F 9/26 (2006.01) G06F 9/42 (2006.01)

Patent

CA 1138118

ABSTRACT OF THE DISCLOSURE In a data processing system whose operation is under the control of firmware words stored in a control store, a technique is provided by which a routine which has been temporarily suspended may be returned to. The address of the last instruction executed in such routine prior to such suspension is stored and the routine is returned to by the use of such stored address with one bit thereof changed in state by use of an inverter. The control store is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs, One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.

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