Noise reducing circuit for ctd delay line

Details Noise reducing circuit for ctd delay line Noise reducing circuit for ctd delay line

H - Electricity

03

H

328/188, 328/31,

H03H 11/26 (2006.01) G11C 27/04 (2006.01) H04S 1/00 (2006.01)

Patent

CA 1140641

ABSTRACT OF THE DISCLOSURE A delay circuit is disclosed which uses a CTD (charge transfer device). The delay circuit has a signal delay circuit made of a CTD, a clock signal generator for driving the CTD, a pre-emphasis circuit for emphasizing a high frequency region of an input signal to the CTD, and a de-emphasis circuit for emphasizing a low frequency region of a signal delayed by the CTD. In this case, the de-emphasis circuit is so formed that it compensates for the characteristic of the pre-emphasis circuit and then makes a total response about flat. A stereophonic sound extending circuit is also disclosed which has a matrix circuit which composes left and right signals L and R and produces signal components R - .DELTA.L and L-.DELTA.R, a CTD delay circuit inserted into either one of left and right signals processing paths a pre-emphases circuit provid- ed at an input stage of the CTD delay circuit, and a de-emphasis circuit provided at a rear stage of the CTD delay circuit.

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