Noise rejecting ttl to cmos input buffer

Details Noise rejecting ttl to cmos input buffer Noise rejecting ttl to cmos input buffer

H - Electricity

03

K

328/128

H03K 19/0185 (2006.01) H03K 3/3565 (2006.01) H03K 19/003 (2006.01)

Patent

CA 2008749

A TTL to CMOS buffer circuit includes a relatively high-speed first inverter path and a second relatively low- speed inverter path connected to the first path and effective to control the operation of the first path inverter so that short-duration positive- or negative-going noise pulses of amplitude up to 2.4 volts do not incorrectly affect the output level.

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