Noise tolerant multiplex system

Details Noise tolerant multiplex system Noise tolerant multiplex system

H - Electricity

04

B

340/101, 363/10.

H04B 3/54 (2006.01) G08C 15/12 (2006.01) H04B 15/00 (2006.01) H04L 25/49 (2006.01) B60R 16/02 (2006.01)

Patent

CA 1135363

D-3,428 C-3,133 NOISE TOLERANT MULTIPLEX SYSTEM Abstract of the Disclosure: A noise tolerant time division multiplex system including a transmitter and receiver, each constructed as a monolithic integrated circuit and interconnected by a serial data wire. Data as well as power is supplied to the transmitter from a plurality of parallel connected input switches. The transmitter includes a parallel in/serial out shift register controlled by timing logic and further includes a tri-state driver for generating a three-level serial output signal indicative of the status of the input switches. The data is generated at a high rate to eliminate any deleterious effects of noise on the system. The receiver chip receives a regulated energizing potential from the transmitter chip over two additional wires, generates a timing signal from the three level signal and loads the data in binary format into a serial in/parallel out shift register. When the data is properly positioned in the receiver register the data is transferred to latches which energize appropriate relays to control the direction of rotation of various motors controlling the seats, windows and door locks of an automobile.

346801

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