G - Physics – 11 – C
Patent
G - Physics
11
C
356/199, 352/82.
G11C 11/40 (2006.01) G11C 16/04 (2006.01) H01L 29/78 (2006.01) H01L 29/792 (2006.01)
Patent
CA 1078517
Abstract of the Disclosure The present invention provides a memory device of the MNOS FET type wherein each of the source region and the drain region contain a high concentration part and a low concentration part. A double layered insulation film under the gate electrode extends between the source region and drain region but contacts only the lower concentration parts thereof, so that acceptor impurity is prevented from mixing into the double layered insulation film from the source region and drain region, thus greatly improving the life (number of repeated uses) of the device.
245948
Kambara Ginjiro
Koike Susumu
Matsuda Toshio
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