Non-volatile ram bit cell

Details Non-volatile ram bit cell Non-volatile ram bit cell

G - Physics

11

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352/82

G11C 11/40 (2006.01) G11C 11/00 (2006.01) G11C 14/00 (2006.01) G11C 16/04 (2006.01) G11C 29/04 (2006.01)

Patent

CA 2019310

A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.

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