Non-volatile semiconductor memory circuits

Details Non-volatile semiconductor memory circuits Non-volatile semiconductor memory circuits

H - Electricity

03

K

328/150

H03K 19/08 (2006.01) G11C 11/40 (2006.01) G11C 14/00 (2006.01)

Patent

CA 1150784

ABSTRACT "Non-volatile Semiconductor Memory Circuits" An NMOS non-volatile latch having N-channel drivers Q1 and Q2 and variable threshold N-channel FATMOS transistors Q3 and Q4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X1 or X2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.

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