Nrz clock and data recovery system employing phase lock loop

Details Nrz clock and data recovery system employing phase lock loop Nrz clock and data recovery system employing phase lock loop

H - Electricity

04

L

H04L 7/00 (2006.01) G11B 20/14 (2006.01) H03L 7/087 (2006.01) H03L 7/089 (2006.01) H03M 5/14 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2061909

29 Abstract of the Disclosure An improved NRZ clock and data recovery system lends itself to integration includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in 2 manner that is independent of analog relays and process and temperature variations. NRZ data is applied to one side of an exclusive-OR sate (6) and a twice delayed (2 4) version of the NRZ data is applied to the other side. The output of the XOR gate (6) a "blivet" signal is applied to a NRZ phase detector (10) comprising two AND sates (12,14), one of which (12) has as its other input a recovered clock signal output of a VCO (20) and the other of which has as its other input an inverted (16) version of the recovered clock signal. The "up" and "down" outputs of the AND sates (10,12) indicate which direction a frequency control signal (26) should change the VCO (20) frequency. A data holding flip-flop (28) whose input is a once delayed (2) version of the NRZ data is clocked with the recovered clock signal. The NRZ frequency detector (50) monitors the state of the recovered clock signal on opposite edges (52, 53) of the blivet to detect too-high (56) too low (55) and good (54) conditions. The results of the detection can be ignored if a lock signal indicates that the phase lock loop is locked. The lock detector (30) consists of a saturating up/down counter (42) that is incremented (38) by one when good blivets (32) occur and is decremented (40) by four when not-good blivets (36) occur.

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