Offset-nulled sample-and-hold amplifier

H - Electricity – 03 – F

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330/103, 330/34

H03F 1/34 (2006.01) H03F 3/45 (2006.01)

Patent

CA 1179408

OFFSET-NULLED SAMPLE-AND-HOLD AMPLIFIER Abstract A high performance operational amplifier 12 circuit 10 nulls the offset voltage by means of switched capacitors (C2, C3) and holds the signal output 18 during the nulling. Switching is in response to two non- overlapping pulse trains ?1, ? 2. During an output valid phase ?1, with the signal input source connected to the inverting input 14 of the amplifier 12, an offset voltage storage capacitor C2 is connected between the non-inverting input 16 and ground. A signal storage capacitor C3 is connected between the output 18 and ground. During a nulling phase ?2, the signal storage capacitor C3 is disconnected from ground and connected between the output 18 and the inverting input 14. The previously grounded side of the offset voltage storage capacitor C2 is switched to the inverting input port 14. The non-inverting input port 16 is grounded. The offset storage capacitor C2 charges to the input offset voltage, while the inverting input 14 is reset to virtual ground. When the circuit 10 is reconnected in the ?1 valid output phase, the offset is compensated by the input offset storage capacitor C2 without the output 18 having been directly connected to the inverting input 14. This makes possible a shorter settling time. Also disclosed as optional is an output offset limiting feedback network 35 for preventing a locking of the circuit 10 which can result from excessive initial offset voltage and a capacitor C4 connected between the input side of the signal hold capacitor C3 and the inverting input 14 to prevent sensitivity to clock leakage.

419149

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