G - Physics – 11 – C
Patent
G - Physics
11
C
352/40, 352/82
G11C 11/24 (2006.01) G11C 5/06 (2006.01) G11C 5/10 (2006.01) G11C 11/40 (2006.01) G11C 11/403 (2006.01) G11C 11/4097 (2006.01)
Patent
CA 1163714
One Device Field Effect Transistor (FET) AC Stable Random Access Memory (RAM) Array Abstract Disclosed is an integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the trans- fer of binary information through the channel region in and out of the capacitive storage region. Each memory cell also has a bit line contact region which is shared with an adjacent memory cell. The word lines are arranged in rows in a substantially equi- distant parallel relationship, each word line pas- sing, in succession, over the storage region of a first one of the memory cells and electrically integral with the gate region of a second one of the memory cells. The column arrangement of memory cells is interdigitated such that the memory cells asso- ciated with a single bit line are arranged in first and second parallel lines along both the left and right sides of each bit line. Thus, the bit line is arranged in a zig-zag configuration alternately contacting memory cells arranged along its left and right side. FI9-79-006
363544
International Business Machines Corporation
Saunders Raymond H.
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