One transistor-one capacitor memory cell

Details One transistor-one capacitor memory cell One transistor-one capacitor memory cell

G - Physics

11

C

352/82.4

G11C 11/24 (2006.01) G11C 11/40 (2006.01)

Patent

CA 1134509

ONE TRANSISTOR-ONE CAPACITOR MEMORY CELL ABSTRACT OF THE DISCLOSURE An integrated circuit memory cell pair having its data lines insulated with respect to the semiconductor substrate at all points other than the point of electrical contact to the transistors of each memory cell. The semiconductor substrate has drain and source regions about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer insulatively disposed relative to the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer provides the gate regions of the transistors and the data lines. The data lines make electrical contact through a self-aligned embedded contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.

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