G - Physics – 06 – F
Patent
G - Physics
06
F
354/223
G06F 11/10 (2006.01)
Patent
CA 1145851
OPTIMIZATION OF ERROR DETECTION AND CORRECTION CIRCUIT By Brewster J. Porcella ABSTRACT OF THE DISCLOSURE There is provided an error detection and correction circuit which is optimized in terms of the operation, part count and the like. This invention includes parity generator circuitry to generate parity signals in accordance with a variation of the Hamming Code in response to the application of a plurality of input data bits. The parity signals are applied to a memory bus during a write cycle. During a read cycle, the parity generators produce a parity error signal, if appropriate, to indicate an error in parity. The error correction circuit receives the data bits from the memory or memory bus along with the parity error signals generated by the parity generator circuit portion. The data signals and parity error signals are gated together and supplied to Exclusive-OR gates. If an error is indicated by the level of the input signal, the Exclusive-OR gate converts the signal thereby correcting the er- roneous data bit. The circuit further provides means for checking the parity of the parity bits, per se, thereby to provide a double bit error check.
358291
Kirby Eades Gale Baker
Sperry Corporation
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