Optimized electronic operation of digital micromirror devices

G - Physics – 02 – B

Patent

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Details

G02B 26/00 (2006.01) G02B 26/02 (2006.01) G02B 26/08 (2006.01)

Patent

CA 2143079

A method for controlling a digital micromirror device resulting in decreased mechanical stress, longer device lifetimes, decreased incidence of spontaneous bit reset, and increased pulse-width modulation accuracy. To reduce the device stress, the bias voltage applied to the mirror may be reduced after the mirror has been latched. To prevent premature mirror changes, the address electrode bias voltage may be reduced after the mirror is driven to the desired position. To ensure that the mirror returns to the neutral position during reset, the mirror bias voltage may be raised from ground potential to approximately halfway between the two addressing voltages during the reset period. To reduce the effects of hinge memory and to ensure that the mirror rotates toward the proper address electrode, the mirror bias voltage may be gradually increased to allow the mirror time to rotate towards the proper address electrode.

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