Optimized instruction storage and distribution for parallel...

Details Optimized instruction storage and distribution for parallel... Optimized instruction storage and distribution for parallel...

G - Physics

06

F

G06F 15/80 (2006.01) G06F 9/38 (2006.01) G06F 9/46 (2006.01) G06F 15/167 (2006.01)

Patent

CA 2254200

A method of improving the utilization of program memory in a multi parallel processor architecture which utilizes an instruction register file (IRF). The IRF is partitioned into two pages and grouping bits are added to the program instructions to designate the fetch cycle to which the instruction belongs. Routing bits are also used to properly route the instructions to the designated processor. The relative position of the routing instruction within the set of instructions is also used to provide routing information.

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