Out-of-cycle error correction apparatus

Details Out-of-cycle error correction apparatus Out-of-cycle error correction apparatus

G - Physics

06

F

354/224

G06F 11/28 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1136282

SPECIFICATION OF ROBERT E. SUELFLOW AND EDWARD M. DROBNY FOR OUT-OF-CYCLE ERROR CORRECTION APPARATUS ABSTRACT OF THE DISCLOSURE This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system. The data group is simultaneously applied to the instruc- tion buffer and to error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execu- tion unit. If no error is tected in the data group, utilization of the data group proceeds uninterrupted. Two three state busses are employed, the first of which is used to transmit memory data to the error detection and correction (EDAC) circuitry to the data output circuits and to transmit input data to the memory. The second data bus transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.

326658

Affiliated with

Also associated with

Rating

Out-of-cycle error correction apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Out-of-cycle error correction apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Out-of-cycle error correction apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-943038