Output buffer circuit

Details Output buffer circuit Output buffer circuit

H - Electricity

03

K

328/95

H03K 5/02 (2006.01) H03K 19/00 (2006.01) H03K 19/0185 (2006.01) H03K 19/08 (2006.01)

Patent

CA 2037158

An output buffer circuit which supplies logic signals at an emitter- coupled-logic (ECL) level is realized by a CMOS process. The logic signals are supplied to the gate electrodes of a first P-channel CMOS transistor and a first N- channel CMOS transistor connected in series, and their common drain output is supplied to a second P-channel CMOS amplifying transistor having an open drain configuration. Between the output terminal of the P-channel CMOS transistor and an external power supply terminal is a first resistor. A voltage regulating means, connected between the output terminal and the external power supply terminal, regulates the output voltage at the output terminal. In the voltage regulating means, a voltage setting circuit produces a desired voltage using the voltage on the external power supply terminal. A control voltage generating circuit uses the desired voltage to generate a control voltage which acts through a regulating driver circuit to regulate the voltage at the output terminal.

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