Output buffer circuit for high-speed logic operation

Details Output buffer circuit for high-speed logic operation Output buffer circuit for high-speed logic operation

H - Electricity

03

K

H03K 19/0185 (2006.01) H03K 19/017 (2006.01)

Patent

CA 2165596

An output buffer circuit is provided, which enables to reduce the delay of a digital output signal with respect to an input digital signal. The output buffer circuit includes first and second FETs serially connected to each other. A gate of the first FET is applied with a first digital input signal. A gate of the second FET is applied with a second digital input signal. The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal is taken out from a connection point of the first and second FETs. The circuit further includes a current source for causing a bias current having the same direction or polarity as that of a drain current of the first FET to flow through the first FET in the pseudo-OFF state. A turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.

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