Over/under dual in-line chip package

Details Over/under dual in-line chip package Over/under dual in-line chip package

H - Electricity

05

K

356/134, 356/21

H05K 1/02 (2006.01) H01L 23/057 (2006.01) H01L 23/498 (2006.01) H01L 23/538 (2006.01)

Patent

CA 1165465

Abstract: The present invention relates to an electronic circuit package for encapsulating and interconnecting two or more semiconductor chips. A vertically stacked array of sub- strate wafers form a support core in which windows are formed for receiving the chips. Device support surfaces and device lead connecting surfaces are exposed by each cavity on one or more of the substrate wafers. Intra- level conductive strips are separately deposited on each lead connecting surface for attachment to the input/output leads of the circuit devices and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins. Inter-level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra- level conductive strips of a different level. In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement.

370651

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