G - Physics – 11 – C
Patent
G - Physics
11
C
356/140, 352/82
G11C 11/40 (2006.01) G11C 15/00 (2006.01) H01L 21/762 (2006.01) H01L 21/8224 (2006.01) H01L 27/02 (2006.01) H01L 27/102 (2006.01) H01L 29/06 (2006.01)
Patent
CA 1188418
OXIDE ISOLATION PROCESS FOR STANDARD RAM/PROM AND LATERAL PNP CELL RAM ABSTRACT An oxide-isolated RAM and PROM process is disclosed wherein a RAM cir- cuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor mate- rial adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by eliminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacture PROMs from vertical NPN transistors. An LVCEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allow- ing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.
418805
Mishra Umeshwar D.
Shideler Jay A.
Fairchild Camera And Instrument Corporation
Smart & Biggar
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