P-type buffer layers for integrated circuits

Details P-type buffer layers for integrated circuits P-type buffer layers for integrated circuits

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H01L 27/00 (2006.01) H01L 21/76 (2006.01) H01L 27/06 (2006.01) H01L 27/08 (2006.01) H01L 29/10 (2006.01) H01L 29/80 (2006.01)

Patent

CA 1315018

P-TYPE BUFFER LAYERS FOR INTEGRATED CIRCUITS Abstract of the Disclosure An integrated circuit having an epitaxial GaAs buffer layer containing p-type dopant is disclosed. The epitaxial p-doped buffer has a lower point defect/impurity density than bulk, melt-grown GaAs buffer layers and a lower carrier mobility than comparable n-doped buffer layers, and forms p-n junctions with n-doped regions of transistors resident on the buffer layer. The buffer sub- stantially reduces interdevice and intradevice parasitic currents as well as sidegating and back- gating. Furthermore, the p-doped epitaxial buffer enhances device isolation.

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