Package for a semiconductor chip

Details Package for a semiconductor chip Package for a semiconductor chip

H - Electricity

01

L

356/172

H01L 23/50 (2006.01) H01L 23/047 (2006.01) H01L 23/495 (2006.01)

Patent

CA 1188010

A PACKAGE FOR A SEMICONDUCTOR CHIP Abstract A package for a semiconductor chip includes as an integral part thereof a frame-shaped multilayer ceramic capacitor. The chip is mounted within the capacitor structure. Conductive portions of the capacitor serve as the terminals and plates of the capacitor and as planar power and ground members for interconnecting an external power supply to the chip. By means of these planar members, power is distributed to the chip in a low- impedance, substantially transient-free manner without utilizing any of the multiple signal leads emanating from the package. Moreover, the signal leads are separated from the ground plane by a low-dielectric-constant material. As a result, the signal leads are minimally loaded and are characterized by a relatively constant impedance selected to optimize signal transfer to and from the chip.

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