H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 23/66 (2006.01) H01L 23/04 (2006.01) H01L 23/055 (2006.01) H01L 23/488 (2006.01) H01L 23/498 (2006.01) H01L 23/50 (2006.01)
Patent
CA 2118785
Abstract of the Disclosure: A package semiconductor device comprises an insulating substrate having an upper surface formed with a plurality of connection pads and an under surface formed with a plurality of external connection members each of which is electrically connected to a corresponding one of the connection pads through a via hole formed through the insulating substrate. An integrated circuit chip is bonded facedown on the upper surface of the insulating substrate so that the integrated circuit chip is electrically connected to the connection pads through solder bumps. An electrically conductive cap is covered on the first surface of the insulating substrate so that the integrated circuit chip is encapsulated in a space defined by the insulating substrate and the conductive cap. A back electrode of the integrated circuit chip is electrically connected to the conductive cap through an electrically conducting element.
Bereskin & Parr
Sumitomo Electric Industries Ltd.
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