Packaging microminiature devices

Details Packaging microminiature devices Packaging microminiature devices

H - Electricity

01

L

356/131, 356/134

H01L 27/04 (2006.01) H01L 23/14 (2006.01) H01L 23/522 (2006.01) H01L 23/538 (2006.01) H01L 23/64 (2006.01)

Patent

CA 1227287

- 17 - PACKAGING MICRO MINIATURE DEVICES Abstract One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

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