Packaging microminiature devices

Details Packaging microminiature devices Packaging microminiature devices

H - Electricity

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L

356/134

H01L 23/52 (2006.01) H01L 23/14 (2006.01) H01L 23/522 (2006.01) H01L 23/538 (2006.01) H01L 23/64 (2006.01) H01L 25/04 (2006.01)

Patent

CA 1232367

- 17 - PACKAGING MICROMINIATURE DEVICES Abstract One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

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