Packet buffer memory with integrated...

Details Packet buffer memory with integrated... Packet buffer memory with integrated...

G - Physics

11

C

G11C 7/10 (2006.01) G06F 12/02 (2006.01) G11C 8/06 (2006.01)

Patent

CA 2425278

A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de- allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.

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