Page memory management in non time critical data buffering...

Details Page memory management in non time critical data buffering... Page memory management in non time critical data buffering...

G - Physics

06

F

G06F 13/16 (2006.01)

Patent

CA 2297496

A primary objective of prior art memory management schemes is to provide rapid access to a table of used/free memory page addresses to facilitate location and allocation of the next available free page as quickly as possible (e.g. within a few hardware clock cycles). But it is not always essential to allocate new pages within the smallest possible number of hardware clock cycles. Furthermore, some tasks need not "see" (or access) more than a few pages (possibly as few as 1 or 2 pages) at a time. By exploiting these factors, the present invention facilitates management of a collection of pages using an address table containing the smallest possible number of bits (i.e. N bits for a memory divided into N pages). The invention also provides a method of accessing a small number of pages via simple multiplexed address selection. The invention is well suited to use in embedded chip applications which pass data through a set of data storage buffers, as is common in a packet switched network environment.

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