Page mode operation of main system memory in a medium scale...

Details Page mode operation of main system memory in a medium scale... Page mode operation of main system memory in a medium scale...

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G11C 8/00 (2006.01) G11C 7/10 (2006.01) G11C 8/12 (2006.01) G11C 8/18 (2006.01)

Patent

CA 1258910

PAGE MODE OPERATION OF MAIN SYSTEM MEMORY IN A MEDIUM SCALE COMPUTER Abstract of the Disclosure A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory array bank associated therewith with each memory array including a plurality of memory elements arranged in rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory array bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.

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