Paged virtual cache system

Details Paged virtual cache system Paged virtual cache system

G - Physics

06

F

354/233, 354/244

G06F 12/08 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1278101

ABSTRACT OF THE DISCLOSURE A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories f or processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

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