Paired instruction processor branch recovery mechanism

Details Paired instruction processor branch recovery mechanism Paired instruction processor branch recovery mechanism

G - Physics

06

F

354/230.71

G06F 9/22 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2016254

PAIRED INSTRUCTION PROCESSOR BRANCH RECOVERY MECHANISM ABSTRACT OF THE DISCLOSURE A mechanism for recovering from a branch misprediction in a processor system that issues a family of more than one instruction during a single clock that determines the location of the branch instruction in the family, completes the data writes for all instructions in the family preceding the branch instruction, inhibits the data writes for all instructions in the family following the branch instruction, and fetches the correct next instruction into the pipeline. T18/10577-212

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