Paired instruction processor precise exception handling...

Details Paired instruction processor precise exception handling... Paired instruction processor precise exception handling...

G - Physics

06

F

354/230.7

G06F 9/22 (2006.01) G06F 9/312 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2016252

PAIRED INSTRUCTION PROCESSOR PRECISE EXCEPTION HANDLING MECHANISM ABSTRACT OF THE DISCLOSURE A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized. T18/10577-211

Affiliated with

Also associated with

Rating

Paired instruction processor precise exception handling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Paired instruction processor precise exception handling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Paired instruction processor precise exception handling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1392174