Pairing of spills for parallel registers

Details Pairing of spills for parallel registers Pairing of spills for parallel registers

G - Physics

06

F

G06F 9/45 (2006.01) G06F 9/30 (2006.01) G06F 12/02 (2006.01)

Patent

CA 2434257

The present invention provides a design for handling register overflow in a parallel register architecture. In an embodiment, spilt code generated by a register allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.

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