Parallel arithmetic-logic unit for use as an element of a...

Details Parallel arithmetic-logic unit for use as an element of a... Parallel arithmetic-logic unit for use as an element of a...

G - Physics

06

E

354/166

G06E 1/00 (2006.01) G06F 7/575 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1292074

ABSTRACT OF THE DISCLOSURE A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator means for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.

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