Parallel associative processor system

G - Physics – 06 – F

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 15/16 (2006.01) G06F 7/57 (2006.01) G06F 9/30 (2006.01) G06F 9/318 (2006.01) G06F 9/38 (2006.01) G06F 15/173 (2006.01) G06F 15/80 (2006.01) F02B 75/02 (2006.01)

Patent

CA 2050166

EN9-90-075 PARALLEL ASSOCIATIVE PROCESSOR SYSTEM ABSTRACT Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip implementation in an air cooled environment. The array provided is an N dimensional array of byte wide processing units each coupled with an adequate segment of byte wide memory and control logic. A partitionable section of the array containing several processing units are contained on a silicon chip arranged with "Picket"s, an element of the processing array preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A Picket Processor system (or Subsystem) comprises an array of pickets, a communication network, an I/O system, and a SIMD controller consisting of a microprocessor, a canned routine processor, and a microcontroller that runs the array.The Picket Architecture for SIMD includes set associative processing, parallel numerically intensive processing with physical array processing similar to image processing a military picket line analogy fits quite well. Pickets, having a bit parallel processing element, with local memory coupled to the processing element for the parallel processing of information in an associative way where each picket is adapted to perform one element of the associative process. We have provided a way for horizontal association with each picket. The memory of the picket units is arranged in an array. The array of pickets thus arranged comprises a set associative memory. The set associative parallel processing system on a single chip permits a smaller set of 'data' out of a larger set to be brought out of memory where an associative operation can be performed on it. This associative operation, typically an exact compare, is performed on the whole set of data in parallel, utilizing the Picket's memory and execution unit.

LandOfFree

Say what you really think

Search LandOfFree.com for Canadian inventors and patents. Rate them and share your experience with other people.

Rating

Parallel associative processor system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel associative processor system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel associative processor system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFCA-PAI-O-1537180

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.