G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 9/48 (2006.01)
Patent
CA 2432384
The invention concerns a parallel electronic architecture comprising a plurality of processing units (1a, 1b, , 1n) connected to a communication bus, each processing unit being designed to automatically execute one or several predefined tasks. Each processing unit is configured such that each of the tasks is associated with a function key, and designed to communicate with the other processing units in accordance with the following protocol: transmission of a message comprising at least a function key characterising a functional capability, and optionally a frame consisting of one or several words; each processing unit is further designed to decode each header passing through the bus, and, on the basis of the value of said function key, to either ignore the message transmitted on the bus, or execute the task associated with said message function key.
L'architecture ~lectronique parall~le comporte une pluralit~ d'unit~s de traitement (1a, 1b,...1n) connect~es ~ un bus de communication, chaque unit~ de traitement ~tant con~ue pour ex~cuter automatiquement une ou plusieurs t~ches pr~d~finies. Chaque unit~ de traitement est configur~e de telle sorte que chacune de ses t~ches est associ~e ~ un en-tÚte, et con~ue pour communiquer avec les autres unit~s de traitement selon le protocole suivant : envoi sur le bus d'un message comportant au moins un en-tÚte caract~risant une fonctionnalit~, et ~ventuellement une trame constitu~e d'un ou plusieurs mots; chaque unit~ de traitement est en outre con~ue pour d~coder chaque en-tÚte transitant sur le bus, et pour, en fonction de la valeur de cet en-tÚte, soit ignorer le message ~mis sur le bus, soit ex~cuter la t~che associ~e ~ l'en- tÚte de ce message.
Lavarec Erwan
Tremel Laurent
Goudreau Gage Dubuc
Wany S.a.
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