H - Electricity – 04 – L
Patent
H - Electricity
04
L
354/229, 354/233
H04L 12/00 (2006.01) G06F 15/80 (2006.01) H04L 29/06 (2006.01) H04L 29/08 (2006.01)
Patent
CA 1313412
FR 9 88 005 ABSTRACT PARALLEL PROCESSING METHOD AND DEVICE FOR RECEIVING AND TRANSMITTING HDLC SDLC BIT STREAMS This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6. (Figure 2)
597345
Calvignac Jean
Feraud Jacques
Naudin Bernard
Pin Claude
Saint-Georges Eric
International Business Machines Corporation
Na
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