Parallel processing state alignment

Details Parallel processing state alignment Parallel processing state alignment

G - Physics

06

F

354/231, 354/233

G06F 15/16 (2006.01) G06F 9/46 (2006.01) G06F 9/48 (2006.01) G06F 15/17 (2006.01)

Patent

CA 1274020

Abstract of the Disclosure Circuitry, and associated methodology, in a parallel processing environment for aligning the various processing states of the autonomous processors communicating over a common bus assures that the order of execution and alignment of processing states is preserved across processors. This is effected by augmenting each processor with a state alignment network for inhibiting, within one interval of the global reference generator, generation of global reference signals. The reference generator is restarted only after all processing is completed in the order required by the allocation of tasks among the processors. To provide maximal efficiency, the state alignment network incorporates an arrangement to detect periods of delay between scheduled tasks and to automatically advance to the next immediate state requiring processing.

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