Parallel processor memory system

Details Parallel processor memory system Parallel processor memory system

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G06F 15/16 (2006.01) G06F 11/10 (2006.01) G06F 13/378 (2006.01) G06F 15/173 (2006.01) G06F 15/80 (2006.01) G06F 11/00 (2006.01)

Patent

CA 2073185

2073185 9110200 PCTABS00006 A massively parallel processor includes a plurality of clusters (40). Each cluster includes processor elements (50.00-50.15) ("PEs") and a cluster memory (54). Each PE (200) has an address register (206), stage register (251), error register (310), enable flag (336) memory flag (338), and grant request flag (211). A cluster data bus (225) and error bus (302, 304) connects each stage register and error register of the cluster to memory (260). The grant request flags of the cluster are interconnected by a polling network (362, 364), which polls one grant request flag at a time. In response to a signal on polling network (362, 364) and the state of the memory flag (338), grant request flag (211) determines an I/O operation between data register (251) and cluster memory (260) over cluster data bus (255). Data and error bits are associated with respective processor elements (200). Sequential memory operations (110 - 113) proceed in parallel with parallel processor operations (102 - 109) and may be queued. In direct address mode, a PE (200) addresses its own address space by appending its PE number (203) to a broadcast partial address furnished over a broadcast bus (250). The PE number (203) is furnished on a cluster address bus (246). In indirect address mode, PE addresses its own address space or that of other PEs in its cluster by locally calculating a partial address, then appending to it its own PE number (203) or that of another PE in its cluster. The full address is furnished over the cluster address bus (246).

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