Parallel processor with redundancy of processor pairs

Details Parallel processor with redundancy of processor pairs Parallel processor with redundancy of processor pairs

G - Physics

06

F

G06F 15/80 (2006.01) G06F 11/20 (2006.01) G06F 15/163 (2006.01)

Patent

CA 2255634

General purpose parallel computer, latency reduction MIMD, with multiple processors and multiple memory address spaces, wherein processors (SPU) are redundantly replicated on each memory (M) bus (C-BUS) and, formed/connected as either master-active or slave-inactive of the bus and to interface a suitable communication structure (A-S) for transferring among themselves the process context and the bus control, in such a way to execute in turn a unique migrant sequential process per bus (C-BUS), and wherein each processor is also directly and tightly coupled with devoted private buses (P-P) to one corresponding processor of another one bus (C-BUS) in a way to form, between distinct buses (C-BUS), biprocessor pairs (DPU) capable of allowing communication and synchronization of the parallel migrant processes.

L'invention concerne un ordinateur parallèle polyvalent, MIMD, à temps de latence réduit, avec de multiples processeurs et de multiples espaces d'adresse en mémoire, dans lequel des processeurs (SPU) sont répliqués par redondance sur chaque bus (C-BUS) mémoire (M) et formés/connectés à titre d'actif maître ou d'inactif esclave du bus, et pour interfacer une structure de communication appropriée (A-S) en vue de transférer parmi eux-mêmes le contexte du processus et la commande du bus, de manière à exécuter ensuite un processus séquentiel migrant unique par bus (C-BUS). Chaque processeur est également couplé directement et étroitement, à l'aide de bus privés spécialisés (P-P), avec un processeur correspondant d'un autre bus (C-BUS) de manière à former, entre des bus distincts (C-BUS), des paires de biprocesseurs (DPU) aptes à permettre la communication et la synchronisation des processus migrants parallèles.

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