Parallel rate control for digital video encoder with...

H - Electricity – 04 – B

Patent

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H04B 1/66 (2006.01) H04J 3/16 (2006.01) H04N 7/12 (2006.01) H04N 11/02 (2006.01)

Patent

CA 2590920

A method of operating a multi-processor video encoder (Fig. 2) by determining a target size corresponding to a preferred number of bits to be used when creating an encoded version of a picture in a group of sequential pictures making up a video sequence (See Fig. 2, item 16). The method includes the steps of calculating a first degree of fullness of a coded picture buffer at a first time (See Fig. 2, item 8), operating on the first degree of fullness to return an estimated second degree of fullness of the coded picture buffer at a second time (See Fig. 2, item 12), and operating on the second degree of fullness to return an initial target sized for the picture (See Fig. 2, item 28). The first time corresponding to the most recent time an accurate degree of fullness of the coded picture buffer can be calculated and the second time occurs after the first time (Fig. 2, items 20 and 28).

L'invention concerne un procédé d'utilisation d'un codeur vidéo à multiples processeurs par détermination d'une taille cible correspondant à un nombre préféré de bits à utiliser lors de la création d'une version codée d'une image dans un groupe d'images séquentielles constituant une séquence vidéo. Le procédé comprend les étapes consistant à calculer un premier degré de remplissage d'un tampon d'images codées à un premier moment, à utiliser le premier degré de remplissage afin de renvoyer un second degré estimé de remplissage du tampon d'images codées à un second moment, et à utiliser le second degré de remplissage afin de renvoyer une cible initiale dimensionnée pour l'image. Le premier moment correspond au moment le plus récent où un degré précis de remplissage du tampon d'images codées peut être calculé et le second moment survient après le premier moment.

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