Parallel register transfer mechanism for a reduction...

Details Parallel register transfer mechanism for a reduction... Parallel register transfer mechanism for a reduction...

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06

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354/237

G06F 12/02 (2006.01) G06F 9/30 (2006.01) G06F 9/315 (2006.01) G06F 9/44 (2006.01) G06F 13/38 (2006.01)

Patent

CA 1235230

-17- ABSTRACT OF THE DISCLOSURE PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.

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