Parallel time slot interchanger matrix and switch block...

H - Electricity – 04 – Q

Patent

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344/25

H04Q 11/04 (2006.01) H04Q 11/08 (2006.01)

Patent

CA 2007312

ABSTRACT OF THE DISCLOSURE A parallel time slot interchanger, particularly for use in telecommunication switching, comprises a plurality of switch groups, with each switch group containing a second plurality of channels. The parallel time slot interchanger incorporates a matrix-type architecture, with each module of the matrix comprising a switch block which in turn incorporates a switch memory, connect memory and associated control circuitry. The connect memory of each switch block is controlled by the control circuity of that block. The data stored in the connect memory contains switch memory address information for reading channel data stored within the switch memory of the same switch block so as to be able to perform a time slot switching function during any given time slot of the parallel time slot interchanger. Each switch block is uniquely identified within its corresponding switch group so that only one switch memory address location is read and output during any time slot for each switch group. An interconnected processor is able to communicate with any switch block so as to update the connect memory data and consequently the pattern of interconnects between channels of the same or different switch group. The parallel time slot interchanger is particularly adapted for implementation with application specific integrated circuitry.

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